Integrated circuits (ICs) typically include a plurality of semiconductor devices and interconnect wiring. Networks of metal interconnect wiring are often used to connect the semiconductor devices from the semiconductor portion of the substrate. Multiple levels of metal interconnect wiring form a plurality of metallization layers above the semiconductor portion of the substrate and are connected together to form a back-end-of-the-line (“BEOL”) interconnect structure. Within such a structure, metal lines in the metallization layers run parallel to the substrate and conductive vias run perpendicular to the substrate between the metallization layers to interconnect the metal lines.
High performance of contemporary ICs may be achieved using a highly conductive metal, such as copper, as the interconnect metal of the BEOL interconnect structure. The BEOL interconnect structure also employs a low dielectric constant (low-k) dielectric material as an interlayer or interlevel dielectric (ILD) layer or layers between and/or about the interconnect metal of the structure.
Conventional fabrication of BEOL interconnect structures include forming an ILD layer of a dielectric material such as porous silicon dioxide overlying a semiconductor substrate. A hard mask layer is then deposited and patterned overlying the ILD layer. Using the patterned hard mask layer as an etch mask, openings including via-holes and metal line trenches are etched into the ILD layer. The via-holes and metal line trenches are then cleaned and filled with a conductive metal to form the conductive vias and metal lines that form part of the BEOL interconnect structure. Any overburden of the conductive metal above the ILD layer is typically removed by a chemical mechanical planarization (CMP) process. Unfortunately, during etching, cleaning, and/or CMP, damage and/or dimensional variations across the wafer can occur to the dielectric material particularly in areas proximate the via-holes and conductive vias, and/or the metal line trenches and metal lines. This can result, for example, in variations in wire resistance of the metal lines and/or reduce chamfer control of the conductive vias.
Additionally, during normal operation of the IC, chip pack interactions (CPI) can occur in which the temperature of the IC will generally increase due to, for example, the relatively large power consumption by the semiconductor devices. This increased temperature can produce relatively high thermal stresses in the IC including in the BEOL interconnect structure due to the thermal expansion differences between the conductive metal(s) and the dielectric material(s) that form the interconnect structure. These relatively high thermal stresses can result in reliability issues resulting from, for example, cracking and/or delamination (e.g., peeling) of or between the various metallization layers.
Accordingly, it is desirable to provide integrated circuits with improved metal resistance uniformity, via chamfer control, and/or robustness to chip package interactions and methods for fabricating such integrated circuits. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.